Address generation units incorporated in processors, such as microprocessors, digital signal processors (DSPs) or the like, are typically designed to support and generate addresses for general purpose applications with different types and structures of complex data memory blocks. Conventional address generation units may employ one of several typical address generation methods.
For example, an address generation unit may use immediate addressing, which forces the instruction to include an immediate operand. This method results in the use of increased power and redundancy in the instruction. Another example often used is indirect addressing in which the data pointed to by a first address is the actual address to be used for the instruction. This method requires a complex hardware implementation that consumes a relatively large amount of power and die area. A third example that is used to generate addresses for multi-buses in some cases employs several pointers, one for each bus, generated based on a single indirect operand. However, this method uses a large instruction width and multiple calculations, resulting in a highly complex instruction.
Thus, none of these typical methods provides a power- and/or area-efficient method for generating addresses for a processor, especially for a processor that uses a multi-bus. Therefore, there is a need in the art for an improved method for generating addresses for processors.